2 thoughts on “GMN68 diagnostic card shows that R2 is not lit, please tell me what the problem is, thank you”

  1. Cecil

    Detailed explanation of the motherboard diagnostic card code (comparison table), special code "00" and "FF" and other starts in three cases:
    ① have appeared after a series of other code: "00" or "ff ", Then the motherboard is ok.
    ② If there is no error in the CMOS settings, the non -serious failure will not affect the continuation of BIOS self -test, and eventually appears "00" or "FF".
    ③ "00" or "FF" or other starting code appeared as soon as it was turned on and the main board was not running.
    2. This table is sorted from small to large according to small value, and the order order in the card is uncertain.
    3. The unarmed code table is not listed.
    4. For different BIOS (commonly used AMI, AWARD, Phoenix), the meaning is different from the same code. Therefore, you should find out which type of BIOS you are detected. You can consult your computer to use The manual, or directly view it from the BIOS chip on the motherboard, you can also see it directly when starting the screen.
    5. There are only a few PCI grooves of the motherboard only appeared, but the ISA slot has a complete self -inspection code output. And at present, the ISA slot output of the ISA slot of the original motherboard has been found, and the PCI slot has a complete code output. Therefore, it is recommended that when checking the code is unsuccessful, replace the dual slot card to another slot to try it to try it. Essence In addition, the different PCI grooves of the same motherboard, some slots have a complete code, such as the Dell810 motherboard, only a PCI slot near the CPU has a complete code display, which has been changed to "00" or "FF", and other PCI slots come to the way to reach "38" does not continue to change.
    6. The time required for the reset signal is not necessarily synchronized with PCI, so ISA may start to issue code, but the PCI's reset light is not extinguished, so the PCI code stops to start code.
    Code comparison table
    00. The configuration of the display system is displayed;
    01 processor test 1, processor status verification, if the test fails, the cycle is infinite. The test of the processor register is about to begin, and the interruption cannot be stopped. The CPU register test is in progress or failure.
    02 determines the type of diagnosis (normal or manufacture). If the keyboard buffer contains data, it will fail. Discontinue non -blocking interruption; starting by delay. CMOS is writing / read is in progress or failure.
    03 Clear the 8042 keyboard controller, and the TESTKBRD command (AAH) is completed. ROM BIOS checking parts are in progress or failure.
    04 to reset the 8042 keyboard controller and verify Testkbrd. Keyboard controller soft reset / power -on test. The test of the programm can be performed or failed.
    05 If you continue to repeat the manufacturing test 1 to 5, you can get 8042 control status. The soft reset / power is determined; the ROM is about to start. DMA was in progress or failure.
    06 makes the circuit film initial preparation. Discontinue videos, singularity, DMA circuit chips, and removing DMA circuit films, all page registers and CMOS shutdown bytes. ROM BIOS has been started, and the sum of the ROM BIOS inspection, and check whether the keyboard buffer is cleared. DMA initial page register read / write test is in progress or failure.
    07 processor test 2 to verify the work of the CPU register. The ROM BIOS inspection is normal, the keyboard buffer has been cleared, and the BAT (basic guarantee test) command is issued to the keyboard. .
    08 make the CMOS timer as initial preparation, and the loop of the timer is updated normally. The BAT command has been issued to the keyboard, and the BAT command is about to be written. The RAM update test is in progress or failure.
    09 EPROM checks and must be approved by zero. Credit the basic guarantee test of the keyboard, and then verify the keyboard command byte. The first 64K RAM test is ongoing.
    0A make the video interface as initial preparation. Send the keyboard command byte code, and the command byte data is about to be written. The first 64K RAM chip or data cable fails and displays.
    0b test 8254 channel 0. Write the keyboard controller command by byte, and the blocking / unlock commands of the pin 23 and 24 of pins will be issued. The first 64K RAM ／ / Puppet logic fails.
    0c test 8254 channel 1. The keyboard controller pins 23 and 24 have been blocked / unlock; the NOP command has been issued. The first 64K RAN address line faults.
    0d 1. Check whether the CPU speed matches the system clock. 2. Check whether the programming value of the control chip conforms to the initial settings. 3. Video channel test, if it fails, the horn. The NOP command has been processed; then test the CMOS to stop the register. The first 64K RAM's amazing failure
    0E test CMOS shutdown byte. CMOS stops the register read / write test; the sum of CMOS inspection will be calculated. Initize the input / output port address.
    0F test expanded CMOS. CMOS tests have been calculated to write the diagnostic bytes; CMOS starts to prepare. .
    10 test DMA channel 0. CMOS has made initial preparation, and the CMOS state register is about to make initial preparation for the date and time. The first 64K RAM failure.
    11 test DMA channel 1. The CMOS state register has been prepared for initial preparation and is about to stop DMA and interrupt controller. The first 64dk RAM is the first.
    12 Test the DMA page register. Discontinue DMA controller 1 and interrupt controller 1 and 2; the video display is about to make the port B as the initial preparation. The first 64dk RAM is the second.
    13 Test 8741 keyboard controller interface. The video display has been discontinued, Port B has been preparations; the automatic detection of the circuit film initialization / memory is about to start. The first 64dk RAM is the third place.
    14 Test the memory renewal trigger circuit. The automatic detection of the circuit film initialization / memory is over; the 8254 timer test is about to start. The first 64dk RAM faults.
    15 Test 64K system memory beginning. The 2nd channel timer was tested half; 8254 passing the second channel timer is about to complete the test. The first 64dk RAM faults.
    16 Establish an interrupt vector table used in 8259. The 2 passage timer test is over; 8254 The 1st channel timer is about to complete the test. The first 64dk RAM is the 6th.
    17 adjust the video input / output work. The first passage timer test is over; The first 64dk RAM is the 7th.
    18 Test video memory. If you install the selected video BIOS, it can be bypassed. The 0 -channel timer test is over; the memory is about to start. The first 64dk RAM failure.
    19 Test the interrupt controller of the 1st channel (8259). The memory has begun, and the memory update will be completed. The first 64dk RAM failure.
    1A Test the interrupt controller of the 2nd channel (8259). The memory update line is being triggered, and the 15 microseconds / disconnection will be checked soon. The first 64dk RAM faults.
    1b test the CMOS battery level. Complete the memory update time 30 microsecond test; the basic 64K memory test is about to start. The first 64dk RAM fault.
    1c test the sum of CMOS inspection. The first 64dk RAM failure.
    1d adjustment CMOS configuration. The first 64dk RAM is 13th in failure.
    1E determine the size of the system memory and compare it with the CMOS value. The first 64dk RAM is 14th in failure.
    1F test 64K memory to up to 640K. The first 64dk RAM fifteen failure.
    20 measures a fixed 8259 interrupt position. Start the basic 64K memory test; the address line is about to test. The subordinate DMA register test is in progress or failure.
    21 Maintain an irreversible interrupt (NMI) bit (inspection of the puppet or input / output channel). Through the address line test; the puppet is about to trigger. The main DMA register test is in progress or failure.
    22 Test the interrupt function of 8259. End triggering spectacle; serial data reading / writing test will begin. The main interrupt shielding register test is in progress or failure.
    23 test protection method 8086 virtual method and 8086 page method. Basic 64K serial data reading / writing test is normal; any adjustment before interrupt vector initialization will begin. The belonging to the interrupted shield test is in progress or failure.
    24 to determine an extension memory above 1MB. Any adjustment before the vector is completed, and the initial preparation of the vector will soon begin. Set the ES section address register registry to the high -end memory.
    25 Test all the memory after the first 64K. The initial preparation of the interrupt vector is completed; the input / output port of the 8042 will be read for the rotation type. The interrupt vector is undergoing or failing.
    26 test protection method. Read the input / output port of 8042; about the rotating type to start making the global data initial preparation. Turn on the A20 address line; make it participate.
    27 Determine the control or shielding RAM of the ultra -high -speed buffer memory. The initial preparation of all 1 data is over; any initial preparation after interrupt vector will be performed. The keyboard controller test is in progress or failure.
    28 determines the control of the ultra -high -speed buffer stuff or a special 8042 keyboard controller. The initial preparation of the interrupt vector is completed; the monochrome method is about to adjust. CMOS power failure / total inspection and computing are in progress.
    29. The monochrome method has been adjusted, and the color method is about to adjust. CMOS configuration validity checks are ongoing.
    2A make the keyboard controller as initial preparation. The color method has been adjusted, and the trigger is about to be triggered before the ROM test. Set the basic memory of 64K.
    2b make the drive drive and controller as initial preparation. Triggering the end of the strangeness; any adjustment required before the optional video ROM test. The screen memory test is in progress or failure.
    2c check the serial port and make it initial preparation. Complete the processing before the video ROM control; the optional video ROM will be viewed and controlled. The screen is initially prepared or failed.
    2d detect parallel ports and make initial preparation. The optional video ROM control is completed, and any other processing control will be performed after the video ROM replies. Scanning test is in progress or failure.
    2E make the hard disk drive and controller as initial preparation. The processing recovery after the video ROM is controlled; if no EGA / VGA is found, it is necessary to perform the display of the display / writing test. The detection video ROM is ongoing.
    2F to detect mathematical collaborators and make it initial preparation. No EGA / VGA was found; .
    30 Establish basic memory and extended memory. Read / write test by the displayed memory; scan check will be performed soon. Think that the screen can work.
    31 detection from C800: 0 to Efff: 0 selects ROM and make it initial preparation. The display of the display of the display / writing test or scanning test failed, and another display of the display / writing test will be performed. The monochrome monitor can work.
    32 pairs of I / O chip programming on the motherboard COM / LTP / FDD / sound device to make it suitable for setting value. Through another display of the display / writing test; it will be scanned by another display. Column monitors (40 columns) can work.
    33. The video display is over; it will begin to use the adjustment switch and the actual card to check the display of the display. Column monitors (80 columns) can work.
    34. The monitor adapter has been tested; The timer ticking test is in progress or failure. 35. Complete the adjustment display method; the data area of ​​BIOS ROM is about to check. The stop testing is in progress or failure.
    36. The BIOS ROM data area has been checked; A -20 in the door circuit fails.
    37. The cursor adjustment of the identification of power information has been completed; The accident interruption in the protection method.
    38. Complete the display of the display of power; the new cursor position is about to read. RAM testing is undergoing or address failure> FFFFH.
    39. Read the saving cursor position, and the reference information string will be displayed soon. .
    3A. Reference information string display is over; information is about to be displayed. Test or failure of the time interval passage 2.
    3B uses OPTI circuit films (just 486) to make the auxiliary ultra -high -speed buffer stuffed as the initial preparation. u003CESC> information has been displayed; virtual methods, memory testing is about to begin. The calendar clock test calculated daily is in progress or failure.
    3C Establish a sign that allows entering CMOS settings. The serial port test is in progress or failure.
    3D initialization keyboard / PS2 mouse / PNP device and total memory node. The parallel port test is in progress or failure.
    3E try to open the L2 high -speed cache. . Mathematics processor testing is in progress or failure.
    40. The test of virtual methods has been started; it is about to be tested from the video memory. Adjust the CPU speed so that it accurately matches the peripheral clock.
    41 interrupt has been opened, which will initialize data for 0: 0 detection memory transformation (interrupt controller or memory poor) recovery from the video deposit inspection; the descriptor table is about to prepare. The system plug -in board chooses to fail.
    42 Display window into setup. The descriptor table is ready; the virtual method is about to perform a memory test. Extend the CMOS RAM failure.
    43 If you plug and use BIOS, the serial port and mouth are initialized. Enter the virtual method; it is about to achieve interruption for the diagnostic method. . 44. Realized interrupt (such as connecting the diagnostic switch; the initial preparation of the data is about to check the memory of the memory at 0: 0.) BIOS interrupt for initialization.
    45 Initialize mathematics processor. The data has been made in initial preparation; the size of the memory is about to return to 0: 0 and find the scale of the system memory. .
    46. Test the storage memory has been returned; the memory size is calculated, and the page will be written to test the memory. Check only the memory ROM version.
    47. The upcoming memory test page; the basic 640K memory is written to the page.
    48. Basic memory has been written to the page; the memory of more than 1MB will be determined. Video inspection, CMOS re -configures.
    49. Find out the memory below 1bm and test; to determine the memory of more than 1MB. .
    4A. Find out the memory of more than 1MB and test; the BIOS ROM data area is about to check. Initialize the video.
    4b. BIOS ROM's data area is over, and the u003CESC> and removing 1MB of memory for the soft residence will be checked. 4C. Remove the memory (soft reset) of more than 1MB (soft reset) to remove more than 1MB of memory. Shielding video BIOS ROM. . 4D. Remove the memory (soft reset) of more than 1MB; the size of the storage memory. .
    4 If there are errors if you detect; display error information on the display, and wait for the customer to press the u003CF1> key to continue. Start memory test: (no soft reset); the test of the first 64K memory is about to display. Show copyright information.
    4F read and write soft and hard disk data for DOS guidance. Start displaying the size of the memory, and the testing memory will be updated; the serial and random memory test will be performed. .
    50 stored the CMOS value in the current BIOS monitoring time zone to CMOS. Complete the memory test below 1MB; the size of the high -speed memory is about to locate and cover it. Send the CPU type and speed to the screen.
    51. Test more than 1MB of memory. .
    52 All ISA reads only memory ROM for initialization, and finally assigns IRQ numbers such as PCI. Complete memory tests of more than 1MB; they are about to return to the real address method. Enter the keyboard detection.
    53 If you are not plugged in BIOS, you can initialize the serial port, meter, and set the value. Save the size of the CPU register and memory, and will enter the real address method. .
    54. The real -site method is successfully opened; Scan the "Strike key"
    55. The register has been restored, and the address line of the door circuit A -20 will be discontinued. .
    56. The address line of the A -20 is successfully discontinued; the BIOS ROM data area is about to check. The keyboard test is over.
    57. The BIOS ROM data area was checked half; continued. .
    58. The data area of ​​the BIOS ROM is over; the u003CESC> information will be removed. Non -setting interrupt test.
    59. u003CESC> information has been cleared; the information has been displayed; the test of DMA and interrupt controller is about to start. .
    5A.. Show the "F2" key.
    5b.. Test the basic memory address.
    5c.. Test 640K basic memory.
    60 Set the hard disk to guide the sector virus protection function. Test through the DMA page register; the video memory is about to test. Test extended memory.
    61 Display the system configuration table. The video storage memory test is over; the DMA # 1 basic register will be performed. .
    62 began to use interrupt 19h for system guidance. Test through DMA # 1 basic registers; the test of DMA # 2 register is about to be performed. Test extended memory address lines.
    63. Test the basic register of DMA # 2; the BIOS ROM data area is about to check. .
    64. The BIOS ROM data area was checked half and continued. .
    65. The BIOS ROM data area is over; the DMA device 1 and 2 will be programmed. .
    66. DMA device 1 and 2 programming is over; The cache registry is optimized.
    67. 8259 The initial preparation is over; the keyboard test is about to start. .
    68.. Make the external cache and CPU internal cache work.
    6a.. Test and display the external cache value.
    6c.. Show the shielded content.
    6e.. Display the attached configuration information.
    70.. The detected error code was sent to the screen display.
    72.. Is there any error in the detection configuration.
    74.. Test the real hour clock.
    76.. Check the keyboard error.
    7a .. Locking the keyboard.
    7c.. Set hardware interrupt vector.
    7e.. Test whether there is a mathematical processor.
    80. At the beginning of the keyboard test, the keyboard is being cleared and checked, and the keyboard is about to restore the keyboard. Turn off the programmable input / output device.
    81. Find the keyboard to the keyboard restoration; the test command of the keyboard control port is about to issue. .
    82. The keyboard controller interface test is over. Detect and install a fixed RS232 interface (serial port).
    83. The command bytes have been written, and the initial preparation of global data has been completed; .
    84. Check the key to check whether the memory is about to be lost with CMOS. Detect and install a fixed parallel port. 85. The size of the memory has been checked; soft errors and passwords or bypass arrangements will be displayed soon. .
    86. Checking passwords; programming before bypass arrangement. Re -open programmable I / O device and test whether there are conflicts for fixed I / O.
    87. Complete the programming before the arrangement; the programming of CMOS will be performed. .
    88. Refuse the screen from the CMOS arrangement program; Initialize the BIOS data area.
    89. Complete programming after completing the arrangement; .
    8A. Display the first screen information. Expand the initialization of the BIOS data area.
    8b. Display information: The main and video BIOS is about to block. .
    8c. Successfully shield the main and video BIOS, and will start the programming of the option after CMOS. Perform the soft drive controller initialization.
    8d. I have arranged for option programming, and then check the mouse and make initial preparation. .
    8e. Test the mouse and complete the initial preparation; it is about to reset the hard and soft disk. .
    8f. Soft disk has been checked. The disk will be made for initial preparation and then equipped with soft disks. .
    90. Soft disk configuration is over; The hard disk controller is initialized.
    91. The test end is over; then the hard disk is configured. Local bus hard disk controller initialization.
    92. The configuration of the hard disk is completed; the data area of ​​the BIOS ROM is about to check. Jump to user path 2.
    93. The data area of ​​BIOS ROM has been checked half; .
    94. The data area of ​​BIOS ROM is checked, that is, the adjustment of the memory is basically adjusted and the size of the memory. Turn off the A -20 address line.
    95. The size of the memory is adjusted according to the support of the mouse and hard disk 47; .
    96. Check the restoration after displaying the memory; the initial preparation before the C800: 0 is selected. The "ES section" registry is cleared.
    97. C800: 0 Observe the end of any initial preparation before the ROM control, and then check and control the ROM. . 98. Select the control of the ROM; the process of any treatment required after any selection ROM replies. Find ROM selection.
    99. Any initial preparation required after the ROM test is selected; the data area or printer basic address of the timer is about to establish a timer. .
    9A. The return operation of the chronograph and the basic address of the printer; that is, adjust the basic address of the RS -232. Shield the ROM selection.
    9b. Return after the basic address of the RS -232; .
    9c. The initial preparation of the initial preparation before testing the processor test is ended; then the associate processor is made for initial preparation. Establish power saving management.
    9d. Associate processor is prepared for initial preparation, and any initial preparation after the collaborative processor test is performed. .
    9e. After completing the initial preparation of the collaborator, check the expansion keyboard, keyboard recognition symbols, and digital locks. Open hardware interrupt.
    9f. Check the extension keyboard, adjust the identification logo, digital lock connection or disconnect, and the keyboard recognition command will be issued. .
    a0. Effect the keyboard recognition command; the keyboard recognition logo is about to restore. Setting time and date.
    a1. The keyboard recognition logo restores; then test the test of high -speed buffer storage. .
    a2. High -speed buffer storage test is over; any soft errors will be displayed soon. Check the keyboard lock.
    a3. The soft error display is complete; the rate of keyboard strike is about to adjust. .
    a4. After adjusting the keyboard's blow rate, the waiting state of the memory is about to formulate. The keyboard repeats the initialization of the input rate.
    a5. The memory waiting state is set; the screen will be cleared. .
    a6. The screen has been cleared; .
    a7. It has been enabled to block non -blocking interruption and amazing. Any initial preparation required to control the optional ROM on E000: 0. .
    a8. Control the initial preparation of ROM before E000: 0, and then control any initial preparation required after E000: 0. Clear the "F2" key prompt.
    a9. From controlling E000: 0 ROM, any initial preparation required to control E000: 0 to control E000: 0. .
    aa. The initial preparation of the initial preparation after the ROM is controlled by E000: 0; the configuration of the system is about to display the system. Scan the "F2" key to strike.
    ac.. Settings.
    ae..
    B0.. Check non -critical errors.
    b2.. Power -powered self -inspection was ready to enter the operating system guidance.
    b4.. The bee ring sound.
    b6.. Detect password settings (optional).
    b8.. Clear all description tables.
    bc.. Clear the verification check value.
    Be's default value enters the control chip, which meets the adjustable binary default value table. Clear the screen (optional).
    BF test CMOS establishment value. . Detecting the virus and prompting data backup.
    C0 initialize a high -speed cache. Use interrupt 19 trial guidance.
    C1 memory self -examination. Find the "55" and "AA" tags in the guidance sector.
    c3 The first 256K memory test. ..
    C5 Copy BIOS from ROM for fast self -inspection. ..
    c6 high -speed cache self -examination. ..
    CA detect Micronies super -speed buffer storage (if existence) and make it initial preparation. ..
    cc off the interrupt interrupt processor. ..
    ee processor unexpected exception. ..
    fff Gives control of the INI19 guidance loading program, the motherboard is OK.

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